Add SSE2 and SSE4.1 linear resamplers

Currently the only way SSE 4.1 is detected is by using __get_cpuid, i.e. with
GCC. Windows' IsProcessorFeaturePresent does not report SSE4.1 capabilities.

9 files changed, 294 insertions, 16 deletions

diff --git a/Alc/ALc.c b/Alc/ALc.c
index 3b3e5397..7c8c2322 100644
--- a/Alc/ALc.c
+++ b/Alc/ALc.c
@@ -909,8 +909,12 @@ static void alc_initconfig(void)
     ReadALConfig();
 
     capfilter = 0;
-#ifdef HAVE_SSE
+#if defined(HAVE_SSE4_1)
+    capfilter |= CPU_CAP_SSE | CPU_CAP_SSE2 | CPU_CAP_SSE4_1;
+#elif defined(HAVE_SSE2)
     capfilter |= CPU_CAP_SSE | CPU_CAP_SSE2;
+#elif defined(HAVE_SSE)
+    capfilter |= CPU_CAP_SSE;
 #endif
 #ifdef HAVE_NEON
     capfilter |= CPU_CAP_NEON;
@@ -940,6 +944,8 @@ static void alc_initconfig(void)
                     capfilter &= ~CPU_CAP_SSE;
                 else if(len == 4 && strncasecmp(str, "sse2", len) == 0)
                     capfilter &= ~CPU_CAP_SSE2;
+                else if(len == 6 && strncasecmp(str, "sse4.1", len) == 0)
+                    capfilter &= ~CPU_CAP_SSE4_1;
                 else if(len == 4 && strncasecmp(str, "neon", len) == 0)
                     capfilter &= ~CPU_CAP_NEON;
                 else
diff --git a/Alc/ALu.c b/Alc/ALu.c
index e661af1d..488a7273 100644
--- a/Alc/ALu.c
+++ b/Alc/ALu.c
@@ -91,6 +91,14 @@ static ResamplerFunc SelectResampler(enum Resampler Resampler, ALuint increment)
         case PointResampler:
             return Resample_point32_C;
         case LinearResampler:
+#ifdef HAVE_SSE4_1
+            if((CPUCapFlags&CPU_CAP_SSE4_1))
+                return Resample_lerp32_SSE41;
+#endif
+#ifdef HAVE_SSE2
+            if((CPUCapFlags&CPU_CAP_SSE2))
+                return Resample_lerp32_SSE2;
+#endif
             return Resample_lerp32_C;
         case CubicResampler:
             return Resample_cubic32_C;
diff --git a/Alc/helpers.c b/Alc/helpers.c
index a0230b7c..ff28bf0d 100644
--- a/Alc/helpers.c
+++ b/Alc/helpers.c
@@ -139,7 +139,11 @@ void FillCPUCaps(ALuint capfilter)
             {
                 caps |= CPU_CAP_SSE;
                 if((cpuinf[0].regs[3]&(1<<26)))
+                {
                     caps |= CPU_CAP_SSE2;
+                    if((cpuinf[0].regs[2]&(1<<19)))
+                        caps |= CPU_CAP_SSE4_1;
+                }
             }
         }
     }
@@ -164,10 +168,13 @@ void FillCPUCaps(ALuint capfilter)
     caps |= CPU_CAP_NEON;
 #endif
 
-    TRACE("Got caps:%s%s%s%s\n", ((caps&CPU_CAP_SSE)?((capfilter&CPU_CAP_SSE)?" SSE":" (SSE)"):""),
-                                 ((caps&CPU_CAP_SSE2)?((capfilter&CPU_CAP_SSE2)?" SSE2":" (SSE2)"):""),
-                                 ((caps&CPU_CAP_NEON)?((capfilter&CPU_CAP_NEON)?" Neon":" (Neon)"):""),
-                                 ((!caps)?" -none-":""));
+    TRACE("Got caps:%s%s%s%s%s\n",
+        ((caps&CPU_CAP_SSE)    ? ((capfilter&CPU_CAP_SSE)    ? " SSE"    : " (SSE)")    : ""),
+        ((caps&CPU_CAP_SSE2)   ? ((capfilter&CPU_CAP_SSE2)   ? " SSE2"   : " (SSE2)")   : ""),
+        ((caps&CPU_CAP_SSE4_1) ? ((capfilter&CPU_CAP_SSE4_1) ? " SSE4.1" : " (SSE4.1)") : ""),
+        ((caps&CPU_CAP_NEON)   ? ((capfilter&CPU_CAP_NEON)   ? " Neon"   : " (Neon)")   : ""),
+        ((!caps) ? " -none-" : "")
+    );
     CPUCapFlags = caps & capfilter;
 }
 
diff --git a/Alc/mixer_defs.h b/Alc/mixer_defs.h
index 04fd1f53..94e0b24f 100644
--- a/Alc/mixer_defs.h
+++ b/Alc/mixer_defs.h
@@ -42,6 +42,12 @@ void MixSend_SSE(ALfloat (*restrict OutBuffer)[BUFFERSIZE], const ALfloat *data,
                  struct MixGainMono *Gain, ALuint Counter, ALuint OutPos,
                  ALuint BufferSize);
 
+/* SSE resamplers */
+const ALfloat *Resample_lerp32_SSE2(const ALfloat *src, ALuint frac, ALuint increment,
+                                    ALfloat *restrict dst, ALuint numsamples);
+const ALfloat *Resample_lerp32_SSE41(const ALfloat *src, ALuint frac, ALuint increment,
+                                     ALfloat *restrict dst, ALuint numsamples);
+
 /* Neon mixers */
 void MixDirect_Hrtf_Neon(ALfloat (*restrict OutBuffer)[BUFFERSIZE], const ALfloat *data,
                          ALuint Counter, ALuint Offset, ALuint OutPos, const ALuint IrSize,
diff --git a/Alc/mixer_sse2.c b/Alc/mixer_sse2.c
new file mode 100644
index 00000000..b1cfa598
--- /dev/null
+++ b/Alc/mixer_sse2.c
@@ -0,0 +1,99 @@
+/**
+ * OpenAL cross platform audio library
+ * Copyright (C) 1999-2014 by authors.
+ * This library is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU Library General Public
+ *  License as published by the Free Software Foundation; either
+ *  version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ *  License along with this library; if not, write to the
+ *  Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ *  Boston, MA  02111-1307, USA.
+ * Or go to http://www.gnu.org/copyleft/lgpl.html
+ */
+
+#include "config.h"
+
+#include <xmmintrin.h>
+#include <emmintrin.h>
+
+#include "alu.h"
+#include "mixer_defs.h"
+
+
+static inline void InitiatePositionArrays(ALuint frac, ALuint increment,
+                                          ALuint *frac_arr, ALuint *pos_arr)
+{
+    ALuint frac_tmp;
+
+    pos_arr[0] = 0;
+    frac_arr[0] = frac;
+
+    frac_tmp = frac_arr[0] + increment;
+    pos_arr[1] = pos_arr[0] + (frac_tmp>>FRACTIONBITS);
+    frac_arr[1] = frac_tmp & FRACTIONMASK;
+
+    frac_tmp = frac_arr[1] + increment;
+    pos_arr[2] = pos_arr[1] + (frac_tmp>>FRACTIONBITS);
+    frac_arr[2] = frac_tmp & FRACTIONMASK;
+
+    frac_tmp = frac_arr[2] + increment;
+    pos_arr[3] = pos_arr[2] + (frac_tmp>>FRACTIONBITS);
+    frac_arr[3] = frac_tmp & FRACTIONMASK;
+}
+
+const ALfloat *Resample_lerp32_SSE2(const ALfloat *src, ALuint frac, ALuint increment,
+                                    ALfloat *restrict dst, ALuint numsamples)
+{
+    const __m128i increment4 = _mm_set1_epi32(increment*4);
+    const __m128 fracOne4 = _mm_set1_ps(1.0f/FRACTIONONE);
+    const __m128i fracMask4 = _mm_set1_epi32(FRACTIONMASK);
+    alignas(16) union { ALuint i[4]; float f[4]; } pos_;
+    alignas(16) union { ALuint i[4]; float f[4]; } frac_;
+    __m128i frac4, pos4;
+    ALuint pos;
+    ALuint i;
+
+    InitiatePositionArrays(frac, increment, frac_.i, pos_.i);
+
+    frac4 = _mm_castps_si128(_mm_load_ps(frac_.f));
+    pos4 = _mm_castps_si128(_mm_load_ps(pos_.f));
+
+    for(i = 0;numsamples-i > 3;i += 4)
+    {
+        const __m128 val1 = _mm_setr_ps(src[pos_.i[0]], src[pos_.i[1]], src[pos_.i[2]], src[pos_.i[3]]);
+        const __m128 val2 = _mm_setr_ps(src[pos_.i[0]+1], src[pos_.i[1]+1], src[pos_.i[2]+1], src[pos_.i[3]+1]);
+
+        /* val1 + (val2-val1)*mu */
+        const __m128 r0 = _mm_sub_ps(val2, val1);
+        const __m128 mu = _mm_mul_ps(_mm_cvtepi32_ps(frac4), fracOne4);
+        const __m128 out = _mm_add_ps(val1, _mm_mul_ps(mu, r0));
+
+        _mm_store_ps(&dst[i], out);
+
+        frac4 = _mm_add_epi32(frac4, increment4);
+        pos4 = _mm_add_epi32(pos4, _mm_srli_epi32(frac4, FRACTIONBITS));
+        frac4 = _mm_and_si128(frac4, fracMask4);
+
+        _mm_store_ps(pos_.f, _mm_castsi128_ps(pos4));
+    }
+
+    pos = pos_.i[0];
+    frac = _mm_cvtsi128_si32(frac4);
+
+    for(;i < numsamples;i++)
+    {
+        dst[i] = lerp(src[pos], src[pos+1], frac * (1.0f/FRACTIONONE));
+
+        frac += increment;
+        pos  += frac>>FRACTIONBITS;
+        frac &= FRACTIONMASK;
+    }
+    return dst;
+}
diff --git a/Alc/mixer_sse41.c b/Alc/mixer_sse41.c
new file mode 100644
index 00000000..958fecec
--- /dev/null
+++ b/Alc/mixer_sse41.c
@@ -0,0 +1,103 @@
+/**
+ * OpenAL cross platform audio library
+ * Copyright (C) 1999-2014 by authors.
+ * This library is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU Library General Public
+ *  License as published by the Free Software Foundation; either
+ *  version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ *  License along with this library; if not, write to the
+ *  Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ *  Boston, MA  02111-1307, USA.
+ * Or go to http://www.gnu.org/copyleft/lgpl.html
+ */
+
+#include "config.h"
+
+#include <xmmintrin.h>
+#include <emmintrin.h>
+#include <smmintrin.h>
+
+#include "alu.h"
+#include "mixer_defs.h"
+
+
+static inline void InitiatePositionArrays(ALuint frac, ALuint increment,
+                                          ALuint *frac_arr, ALuint *pos_arr)
+{
+    ALuint frac_tmp;
+
+    pos_arr[0] = 0;
+    frac_arr[0] = frac;
+
+    frac_tmp = frac_arr[0] + increment;
+    pos_arr[1] = pos_arr[0] + (frac_tmp>>FRACTIONBITS);
+    frac_arr[1] = frac_tmp & FRACTIONMASK;
+
+    frac_tmp = frac_arr[1] + increment;
+    pos_arr[2] = pos_arr[1] + (frac_tmp>>FRACTIONBITS);
+    frac_arr[2] = frac_tmp & FRACTIONMASK;
+
+    frac_tmp = frac_arr[2] + increment;
+    pos_arr[3] = pos_arr[2] + (frac_tmp>>FRACTIONBITS);
+    frac_arr[3] = frac_tmp & FRACTIONMASK;
+}
+
+const ALfloat *Resample_lerp32_SSE41(const ALfloat *src, ALuint frac, ALuint increment,
+                                     ALfloat *restrict dst, ALuint numsamples)
+{
+    const __m128i increment4 = _mm_set1_epi32(increment*4);
+    const __m128 fracOne4 = _mm_set1_ps(1.0f/FRACTIONONE);
+    const __m128i fracMask4 = _mm_set1_epi32(FRACTIONMASK);
+    alignas(16) union { ALuint i[4]; float f[4]; } pos_;
+    alignas(16) union { ALuint i[4]; float f[4]; } frac_;
+    __m128i frac4, pos4;
+    ALuint pos;
+    ALuint i;
+
+    InitiatePositionArrays(frac, increment, frac_.i, pos_.i);
+
+    frac4 = _mm_castps_si128(_mm_load_ps(frac_.f));
+    pos4 = _mm_castps_si128(_mm_load_ps(pos_.f));
+
+    for(i = 0;i < numsamples-3;i += 4)
+    {
+        const __m128 val1 = _mm_setr_ps(src[pos_.i[0]], src[pos_.i[1]], src[pos_.i[2]], src[pos_.i[3]]);
+        const __m128 val2 = _mm_setr_ps(src[pos_.i[0]+1], src[pos_.i[1]+1], src[pos_.i[2]+1], src[pos_.i[3]+1]);
+
+        /* val1 + (val2-val1)*mu */
+        const __m128 r0 = _mm_sub_ps(val2, val1);
+        const __m128 mu = _mm_mul_ps(_mm_cvtepi32_ps(frac4), fracOne4);
+        const __m128 out = _mm_add_ps(val1, _mm_mul_ps(mu, r0));
+
+        _mm_store_ps(&dst[i], out);
+
+        frac4 = _mm_add_epi32(frac4, increment4);
+        pos4 = _mm_add_epi32(pos4, _mm_srli_epi32(frac4, FRACTIONBITS));
+        frac4 = _mm_and_si128(frac4, fracMask4);
+
+        pos_.i[0] = _mm_extract_epi32(pos4, 0);
+        pos_.i[1] = _mm_extract_epi32(pos4, 1);
+        pos_.i[2] = _mm_extract_epi32(pos4, 2);
+        pos_.i[3] = _mm_extract_epi32(pos4, 3);
+    }
+
+    pos = pos_.i[0];
+    frac = _mm_cvtsi128_si32(frac4);
+
+    for(;i < numsamples;i++)
+    {
+        dst[i] = lerp(src[pos], src[pos+1], frac * (1.0f/FRACTIONONE));
+
+        frac += increment;
+        pos  += frac>>FRACTIONBITS;
+        frac &= FRACTIONMASK;
+    }
+    return dst;
+}
diff --git a/CMakeLists.txt b/CMakeLists.txt
index bc0f51d4..af41c001 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -300,17 +300,21 @@ ELSE()
 ENDIF()
 
 SET(SSE_SWITCH "")
-IF(MSVC)
-    CHECK_C_COMPILER_FLAG(/arch:SSE HAVE_ARCHSSE_SWITCH)
-    IF(HAVE_ARCHSSE_SWITCH)
-        SET(SSE_SWITCH "/arch:SSE")
-    ENDIF()
-ENDIF()
-IF(NOT SSE_SWITCH)
+SET(SSE2_SWITCH "")
+SET(SSE4_1_SWITCH "")
+IF(NOT MSVC)
     CHECK_C_COMPILER_FLAG(-msse HAVE_MSSE_SWITCH)
     IF(HAVE_MSSE_SWITCH)
         SET(SSE_SWITCH "-msse")
     ENDIF()
+    CHECK_C_COMPILER_FLAG(-msse2 HAVE_MSSE2_SWITCH)
+    IF(HAVE_MSSE2_SWITCH)
+        SET(SSE2_SWITCH "-msse2")
+    ENDIF()
+    CHECK_C_COMPILER_FLAG(-msse4.1 HAVE_MSSE4_1_SWITCH)
+    IF(HAVE_MSSE4_1_SWITCH)
+        SET(SSE4_1_SWITCH "-msse4.1")
+    ENDIF()
 ENDIF()
 
 CHECK_C_SOURCE_COMPILES("int foo(const char *str, ...) __attribute__((format(printf, 1, 2)));
@@ -546,14 +550,16 @@ SET(ALC_OBJS  Alc/ALc.c
 
 
 SET(CPU_EXTS "Default")
-SET(HAVE_SSE  0)
+SET(HAVE_SSE 0)
+SET(HAVE_SSE2 0)
+SET(HAVE_SSE4_1 0)
 SET(HAVE_NEON 0)
 
 # Check for SSE support
-OPTION(ALSOFT_REQUIRE_SSE "Require SSE/SSE2 support" OFF)
+OPTION(ALSOFT_REQUIRE_SSE "Require SSE support" OFF)
 CHECK_INCLUDE_FILE(xmmintrin.h HAVE_XMMINTRIN_H "${SSE_SWITCH}")
 IF(HAVE_XMMINTRIN_H)
-    OPTION(ALSOFT_CPUEXT_SSE "Enable SSE/SSE2 support" ON)
+    OPTION(ALSOFT_CPUEXT_SSE "Enable SSE support" ON)
     IF(ALSOFT_CPUEXT_SSE)
         IF(ALIGN_DECL OR HAVE_C11_ALIGNAS)
             SET(HAVE_SSE 1)
@@ -570,6 +576,46 @@ IF(ALSOFT_REQUIRE_SSE AND NOT HAVE_SSE)
     MESSAGE(FATAL_ERROR "Failed to enabled required SSE CPU extensions")
 ENDIF()
 
+OPTION(ALSOFT_REQUIRE_SSE2 "Require SSE2 support" OFF)
+CHECK_INCLUDE_FILE(emmintrin.h HAVE_EMMINTRIN_H "${SSE2_SWITCH}")
+IF(HAVE_EMMINTRIN_H)
+    OPTION(ALSOFT_CPUEXT_SSE2 "Enable SSE2 support" ON)
+    IF(ALSOFT_CPUEXT_SSE2)
+        IF(ALIGN_DECL OR HAVE_C11_ALIGNAS)
+            SET(HAVE_SSE2 1)
+            SET(ALC_OBJS  ${ALC_OBJS} Alc/mixer_sse2.c)
+            IF(SSE2_SWITCH)
+                SET_SOURCE_FILES_PROPERTIES(Alc/mixer_sse2.c PROPERTIES
+                                            COMPILE_FLAGS "${SSE2_SWITCH}")
+            ENDIF()
+            SET(CPU_EXTS "${CPU_EXTS}, SSE2")
+        ENDIF()
+    ENDIF()
+ENDIF()
+IF(ALSOFT_REQUIRE_SSE2 AND NOT HAVE_SSE2)
+    MESSAGE(FATAL_ERROR "Failed to enable required SSE2 CPU extensions")
+ENDIF()
+
+OPTION(ALSOFT_REQUIRE_SSE4_1 "Require SSE4.1 support" OFF)
+CHECK_INCLUDE_FILE(smmintrin.h HAVE_SMMINTRIN_H "${SSE4_1_SWITCH}")
+IF(HAVE_SMMINTRIN_H)
+    OPTION(ALSOFT_CPUEXT_SSE4_1 "Enable SSE4.1 support" ON)
+    IF(ALSOFT_CPUEXT_SSE4_1)
+        IF(ALIGN_DECL OR HAVE_C11_ALIGNAS)
+            SET(HAVE_SSE4_1 1)
+            SET(ALC_OBJS  ${ALC_OBJS} Alc/mixer_sse41.c)
+            IF(SSE4_1_SWITCH)
+                SET_SOURCE_FILES_PROPERTIES(Alc/mixer_sse41.c PROPERTIES
+                                            COMPILE_FLAGS "${SSE4_1_SWITCH}")
+            ENDIF()
+            SET(CPU_EXTS "${CPU_EXTS}, SSE4.1")
+        ENDIF()
+    ENDIF()
+ENDIF()
+IF(ALSOFT_REQUIRE_SSE4_1 AND NOT HAVE_SSE4_1)
+    MESSAGE(FATAL_ERROR "Failed to enable required SSE4.1 CPU extensions")
+ENDIF()
+
 # Check for ARM Neon support
 OPTION(ALSOFT_REQUIRE_NEON "Require ARM Neon support" OFF)
 CHECK_INCLUDE_FILE(arm_neon.h HAVE_ARM_NEON_H)
diff --git a/OpenAL32/Include/alMain.h b/OpenAL32/Include/alMain.h
index 57b08113..232c438c 100644
--- a/OpenAL32/Include/alMain.h
+++ b/OpenAL32/Include/alMain.h
@@ -887,7 +887,8 @@ extern ALuint CPUCapFlags;
 enum {
     CPU_CAP_SSE    = 1<<0,
     CPU_CAP_SSE2   = 1<<1,
-    CPU_CAP_NEON   = 1<<2,
+    CPU_CAP_SSE4_1 = 1<<2,
+    CPU_CAP_NEON   = 1<<3,
 };
 
 void FillCPUCaps(ALuint capfilter);
diff --git a/config.h.in b/config.h.in
index 090c00ae..3fdc0c7e 100644
--- a/config.h.in
+++ b/config.h.in
@@ -25,6 +25,8 @@
 
 /* Define if we have SSE CPU extensions */
 #cmakedefine HAVE_SSE
+#cmakedefine HAVE_SSE2
+#cmakedefine HAVE_SSE4_1
 
 /* Define if we have ARM Neon CPU extensions */
 #cmakedefine HAVE_NEON