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authorChris Robinson <[email protected]>2015-10-11 06:38:00 -0700
committerChris Robinson <[email protected]>2015-10-11 06:38:00 -0700
commit0211831858fe42b5a95f6992bbdc3d925d589a75 (patch)
tree7845ccbc2388623fe0a2aeebf0eb91d1fb2613ca /Alc/helpers.c
parent75d8e5989f737326b216b46e0a5184501fc8315f (diff)
Move the FIR4 from SSE2 to SSE3
SSE3 can avoid the slow _MM_TRANSPOSE_PS4 call thanks to the inclusion of horizontal adds.
Diffstat (limited to 'Alc/helpers.c')
-rw-r--r--Alc/helpers.c24
1 files changed, 18 insertions, 6 deletions
diff --git a/Alc/helpers.c b/Alc/helpers.c
index dac29296..c789a426 100644
--- a/Alc/helpers.c
+++ b/Alc/helpers.c
@@ -152,8 +152,12 @@ void FillCPUCaps(ALuint capfilter)
if((cpuinf[0].regs[3]&(1<<26)))
{
caps |= CPU_CAP_SSE2;
- if((cpuinf[0].regs[2]&(1<<19)))
- caps |= CPU_CAP_SSE4_1;
+ if((cpuinf[0].regs[2]&(1<<0)))
+ {
+ caps |= CPU_CAP_SSE3;
+ if((cpuinf[0].regs[2]&(1<<19)))
+ caps |= CPU_CAP_SSE4_1;
+ }
}
}
}
@@ -196,8 +200,12 @@ void FillCPUCaps(ALuint capfilter)
if((cpuinf[0].regs[3]&(1<<26)))
{
caps |= CPU_CAP_SSE2;
- if((cpuinf[0].regs[2]&(1<<19)))
- caps |= CPU_CAP_SSE4_1;
+ if((cpuinf[0].regs[2]&(1<<0)))
+ {
+ caps |= CPU_CAP_SSE3;
+ if((cpuinf[0].regs[2]&(1<<19)))
+ caps |= CPU_CAP_SSE4_1;
+ }
}
}
}
@@ -206,7 +214,10 @@ void FillCPUCaps(ALuint capfilter)
/* Assume support for whatever's supported if we can't check for it */
#if defined(HAVE_SSE4_1)
#warning "Assuming SSE 4.1 run-time support!"
- caps |= CPU_CAP_SSE | CPU_CAP_SSE2 | CPU_CAP_SSE4_1;
+ caps |= CPU_CAP_SSE | CPU_CAP_SSE2 | CPU_CAP_SSE3 | CPU_CAP_SSE4_1;
+#elif defined(HAVE_SSE3)
+#warning "Assuming SSE 3 run-time support!"
+ caps |= CPU_CAP_SSE | CPU_CAP_SSE2 | CPU_CAP_SSE3;
#elif defined(HAVE_SSE2)
#warning "Assuming SSE 2 run-time support!"
caps |= CPU_CAP_SSE | CPU_CAP_SSE2;
@@ -220,9 +231,10 @@ void FillCPUCaps(ALuint capfilter)
caps |= CPU_CAP_NEON;
#endif
- TRACE("Extensions:%s%s%s%s%s\n",
+ TRACE("Extensions:%s%s%s%s%s%s\n",
((capfilter&CPU_CAP_SSE) ? ((caps&CPU_CAP_SSE) ? " +SSE" : " -SSE") : ""),
((capfilter&CPU_CAP_SSE2) ? ((caps&CPU_CAP_SSE2) ? " +SSE2" : " -SSE2") : ""),
+ ((capfilter&CPU_CAP_SSE3) ? ((caps&CPU_CAP_SSE3) ? " +SSE3" : " -SSE3") : ""),
((capfilter&CPU_CAP_SSE4_1) ? ((caps&CPU_CAP_SSE4_1) ? " +SSE4.1" : " -SSE4.1") : ""),
((capfilter&CPU_CAP_NEON) ? ((caps&CPU_CAP_NEON) ? " +Neon" : " -Neon") : ""),
((!capfilter) ? " -none-" : "")